A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

Shuai Shao; Youhua Shi; Wentao Dai; Jianyi Meng; Weiwei Shan

doi:10.1109/EDSSC.2015.7285066

A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

Shuai Shao, Youhua Shi, Wentao Dai, Jianyi Meng, Weiwei Shan^*

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm². The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.

Original language	English
Title of host publication	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	126-129
Number of pages	4
ISBN (Electronic)	9781479983636
DOIs	https://doi.org/10.1109/EDSSC.2015.7285066
Publication status	Published - 2015 Sept 30
Event	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore Duration: 2015 Jun 1 → 2015 Jun 4

Publication series

Name	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

Other

Other	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Country/Territory	Singapore
City	Singapore
Period	15/6/1 → 15/6/4

Keywords

Adaptive voltage scaling
time-to-digital converter
universal delay monitor
variation resilient

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2015.7285066

Cite this

Shao, S., Shi, Y., Dai, W., Meng, J., & Shan, W. (2015). A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 126-129). Article 7285066 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285066

A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. / Shao, Shuai; Shi, Youhua; Dai, Wentao et al.
Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 126-129 7285066 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shao, S, Shi, Y, Dai, W, Meng, J & Shan, W 2015, A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. in Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015., 7285066, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 126-129, 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Singapore, Singapore, 15/6/1. https://doi.org/10.1109/EDSSC.2015.7285066

Shao S, Shi Y, Dai W, Meng J, Shan W. A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 126-129. 7285066. (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015). doi: 10.1109/EDSSC.2015.7285066

Shao, Shuai ; Shi, Youhua ; Dai, Wentao et al. / A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 126-129 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015).

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abstract = "A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm2. The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.",

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note = "Funding Information: Acknowledgment: This paper is supported by Qinglan Project and Open Research funding of State Key Laboratory of ASIC and System, Fudan University (2015KF010). Publisher Copyright: {\textcopyright} 2015 IEEE.; 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 ; Conference date: 01-06-2015 Through 04-06-2015",

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AU - Shan, Weiwei

N1 - Funding Information: Acknowledgment: This paper is supported by Qinglan Project and Open Research funding of State Key Laboratory of ASIC and System, Fudan University (2015KF010). Publisher Copyright: © 2015 IEEE.

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N2 - A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm2. The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.

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A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

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