A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Shen Li; Xianghui Wei; Takeshi Ikenaga; Satoshi Goto

doi:10.1145/1228784.1228795

A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Shen Li^*, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k gates@200MHz, with TSMC CMOS 0.18m technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

Original language	English
Title of host publication	GLSVLSI'07
Subtitle of host publication	Proceedings of the 2007 ACM Great Lakes Symposium on VLSI
Pages	20-24
Number of pages	5
DOIs	https://doi.org/10.1145/1228784.1228795
Publication status	Published - 2007
Event	17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy Duration: 2007 Mar 11 → 2007 Mar 13

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	17th Great Lakes Symposium on VLSI, GLSVLSI'07
Country/Territory	Italy
City	Stresa-Lago Maggiore
Period	07/3/11 → 07/3/13

Keywords

Fast intra prediction mode decision
H.264
VLSI architecture

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/1228784.1228795

Cite this

A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. / Li, Shen; Wei, Xianghui; Ikenaga, Takeshi et al.
GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI. 2007. p. 20-24 1228795 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, S, Wei, X, Ikenaga, T & Goto, S 2007, A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. in GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI., 1228795, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 20-24, 17th Great Lakes Symposium on VLSI, GLSVLSI'07, Stresa-Lago Maggiore, Italy, 07/3/11. https://doi.org/10.1145/1228784.1228795

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AB - The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k gates@200MHz, with TSMC CMOS 0.18m technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

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A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Abstract

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Keywords

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