A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song; Zhenyu Liu; Takeshi Ikenaga; Satoshi Goto

doi:10.1093/ietfec/e89-a.12.3594

A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song^*, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 μm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25°C), a clock frequency of 266 MHz can be achieved.

Original language	English
Pages (from-to)	3594-3601
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E89-A
Issue number	12
DOIs	https://doi.org/10.1093/ietfec/e89-a.12.3594
Publication status	Published - 2006 Dec

Keywords

H.264/AVC
Memory organization
Variable block size motion estimation (VBSME)

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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10.1093/ietfec/e89-a.12.3594

Cite this

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AB - A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 μm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25°C), a clock frequency of 266 MHz can be achieved.

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A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Abstract

Keywords

ASJC Scopus subject areas

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