Accuracy-configurable low-power approximate floating-point multiplier based on mantissa bit segmentation

Jie Li, Yi Guo, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)


Nowadays, in energy-efficient design of digital systems, approximate computing (AC) has an increasingly important role. Due to human perceptual limitations, redundancy in input data and so on, there is a huge amount of applications that can tolerate errors. In this paper, an accuracy-configurable approximate floating-point (FP) multiplier is proposed to improve hardware consumption for such applications. Mantissa is divided into a short exactly processed part and a remaining approximately processed part. A new addition and shifting method is applied to the approximate part to replace multiplication to improve hardware performance. Experimental results show the 4-bit exact part configuration of the proposed work ensures the accuracy of 99.17% (MRED is 0.83%) with the reduction 67.65% of area, 16.64% of delay and 75.62% of power. The proposed work also shows good performance in image processing and neural networks.

Original languageEnglish
Title of host publication2020 IEEE Region 10 Conference, TENCON 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9781728184555
Publication statusPublished - 2020 Nov 16
Event2020 IEEE Region 10 Conference, TENCON 2020 - Virtual, Osaka, Japan
Duration: 2020 Nov 162020 Nov 19

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON
ISSN (Print)2159-3442
ISSN (Electronic)2159-3450


Conference2020 IEEE Region 10 Conference, TENCON 2020
CityVirtual, Osaka


  • Accuracy-configurable
  • Approximate computing
  • Bit segmentation
  • Floating-point multiplier
  • High accuracy
  • Low-power

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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