Accuracy-configurable low-power approximate floating-point multiplier based on mantissa bit segmentation

Nowadays, in energy-efficient design of digital systems, approximate computing (AC) has an increasingly important role. Due to human perceptual limitations, redundancy in input data and so on, there is a huge amount of applications that can tolerate errors. In this paper, an accuracy-configurable approximate floating-point (FP) multiplier is proposed to improve hardware consumption for such applications. Mantissa is divided into a short exactly processed part and a remaining approximately processed part. A new addition and shifting method is applied to the approximate part to replace multiplication to improve hardware performance. Experimental results show the 4-bit exact part configuration of the proposed work ensures the accuracy of 99.17% (MRED is 0.83%) with the reduction 67.65% of area, 16.64% of delay and 75.62% of power. The proposed work also shows good performance in image processing and neural networks.