An 18.5ns 128Mb SOI DRAM with a floating body cell

Takashi Ohsawa; Katsuyuki Fujita; Kosuke Hatsuda; Tomoki Higashi; Mutsuo Morikado; Yoshihiro Minami; Tomoaki Shino; Hiroomi Nakajima; Kazumi Inoh; Takeshi Hamamoto; Shigeyoshi Watanabe

An 18.5ns 128Mb SOI DRAM with a floating body cell

Takashi Ohsawa^*, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.

Original language	English
Article number	25.1
Pages (from-to)	376-377+694
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
Publication status	Published - 2005 Dec 6
Externally published	Yes
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2005 Feb 6 → 2005 Feb 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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T1 - An 18.5ns 128Mb SOI DRAM with a floating body cell

AU - Ohsawa, Takashi

AU - Fujita, Katsuyuki

AU - Hatsuda, Kosuke

AU - Higashi, Tomoki

AU - Morikado, Mutsuo

AU - Minami, Yoshihiro

AU - Shino, Tomoaki

AU - Nakajima, Hiroomi

AU - Inoh, Kazumi

AU - Hamamoto, Takeshi

AU - Watanabe, Shigeyoshi

PY - 2005/12/6

Y1 - 2005/12/6

N2 - A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.

AB - A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.

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M3 - Conference article

AN - SCOPUS:28144451149

SN - 0193-6530

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JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

M1 - 25.1

T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

ER -

An 18.5ns 128Mb SOI DRAM with a floating body cell

Abstract

ASJC Scopus subject areas

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