TY - GEN
T1 - An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler
AU - Ito, Masayuki
AU - Hattori, Toshihiro
AU - Yoshida, Yutaka
AU - Hayase, Kiyoshi
AU - Hayashi, Tomoichi
AU - Nishii, Osamu
AU - Yasu, Yoshihiko
AU - Hasegawa, Atsushi
AU - Takada, Masashi
AU - Ito, Masaki
AU - Mizuno, Hiroyuki
AU - Uchiyama, Kunio
AU - Odaka, Toshihiko
AU - Shirako, Jun
AU - Mase, Masayoshi
AU - Kimura, Keiji
AU - Kasahara, Hironori
PY - 2008
Y1 - 2008
N2 - A 104.8mm2 90nm CMOS 600MHz SoC integrates 8 processor cores and 8 user RAMs in 17 separate power domains and delivers 33.6GFLOPS. An automatic parallelizing compiler assigns tasks to each CPU and controls its power mode including power supply in accordance with its processing load and status. The compiler also uses barrier registers to achieve fast and accurate CPU synchronization.
AB - A 104.8mm2 90nm CMOS 600MHz SoC integrates 8 processor cores and 8 user RAMs in 17 separate power domains and delivers 33.6GFLOPS. An automatic parallelizing compiler assigns tasks to each CPU and controls its power mode including power supply in accordance with its processing load and status. The compiler also uses barrier registers to achieve fast and accurate CPU synchronization.
UR - http://www.scopus.com/inward/record.url?scp=49549086225&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=49549086225&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2008.4523071
DO - 10.1109/ISSCC.2008.4523071
M3 - Conference contribution
AN - SCOPUS:49549086225
SN - 9781424420100
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 89
EP - 91
BT - 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2008 IEEE International Solid State Circuits Conference, ISSCC
Y2 - 3 February 2008 through 7 February 2008
ER -