An adder-segmentation-based FIR for high speed signal processing

Jinghao Ye; Masao Yanagisawa; Youhua Shi

doi:10.1109/ASICON47005.2019.8983612

An adder-segmentation-based FIR for high speed signal processing

Jinghao Ye, Masao Yanagisawa, Youhua Shi

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.

Original language	English
Title of host publication	Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
Editors	Fan Ye, Ting-Ao Tang
Publisher	IEEE Computer Society
ISBN (Electronic)	9781728107356
DOIs	https://doi.org/10.1109/ASICON47005.2019.8983612
Publication status	Published - 2019 Oct
Event	13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China Duration: 2019 Oct 29 → 2019 Nov 1

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	13th IEEE International Conference on ASIC, ASICON 2019
Country/Territory	China
City	Chongqing
Period	19/10/29 → 19/11/1

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON47005.2019.8983612

Cite this

An adder-segmentation-based FIR for high speed signal processing. / Ye, Jinghao; Yanagisawa, Masao ; Shi, Youhua.
Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019. ed. / Fan Ye; Ting-Ao Tang. IEEE Computer Society, 2019. 8983612 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ye, J, Yanagisawa, M & Shi, Y 2019, An adder-segmentation-based FIR for high speed signal processing. in F Ye & T-A Tang (eds), Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019., 8983612, Proceedings of International Conference on ASIC, IEEE Computer Society, 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, 19/10/29. https://doi.org/10.1109/ASICON47005.2019.8983612

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title = "An adder-segmentation-based FIR for high speed signal processing",

abstract = "An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.",

author = "Jinghao Ye and Masao Yanagisawa and Youhua Shi",

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year = "2019",

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N2 - An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.

AB - An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.

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M3 - Conference contribution

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BT - Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019

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An adder-segmentation-based FIR for high speed signal processing

Abstract

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