An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

Li Ding; Jing Wang; Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue

doi:10.1109/ISCAS.2013.6572194

An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Pages	1712-1715
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2013.6572194
Publication status	Published - 2013
Event	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing Duration: 2013 May 19 → 2013 May 23

Other

Other	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
City	Beijing
Period	13/5/19 → 13/5/23

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2013.6572194

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Ding, L, Wang, J, Huang, Z, Kurokawa, A & Inoue, Y 2013, An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. in Proceedings - IEEE International Symposium on Circuits and Systems., 6572194, pp. 1712-1715, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, 13/5/19. https://doi.org/10.1109/ISCAS.2013.6572194

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abstract = "The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.",

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AB - The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.

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ER -

An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

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