An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/APCCAS.2014.7032779

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

As process technologies advance, the importance of timing error correction techniques is increasing as well. In this paper, We propose an area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction circuits (STEPCs). STEPC predicts timing errors by monitoring the middle points of several speed-paths in a circuit. However, we need many STEPCs with a high area overhead to predict timing errors in an overall circuit. Our proposed method moves the STEPC insertion positions to minimize the number of inserted STEPCs. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs. Our proposed algorithm reduces the required number of STEPCs to 1/19 and their area to 1/5 compared with a naive algorithm. Furthermore, our algorithm realizes 2.25X overclocking compared with just inserting STEPCs into several speed-paths.

Original language	English
Title of host publication	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	300-303
Number of pages	4
Edition	February
ISBN (Electronic)	9781479952304
DOIs	https://doi.org/10.1109/APCCAS.2014.7032779
Publication status	Published - 2015 Feb 5
Event	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan Duration: 2014 Nov 17 → 2014 Nov 20

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Number	February
Volume	2015-February

Other

Other	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Country/Territory	Japan
City	Ishigaki Island, Okinawa
Period	14/11/17 → 14/11/20

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2014.7032779

Cite this

Yoshida, S., Shi, Y., Yanagisawa, M., & Togawa, N. (2015). An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 (February ed., pp. 300-303). Article 7032779 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032779

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. / Yoshida, Shinnosuke; Shi, Youhua ; Yanagisawa, Masao et al.
2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 300-303 7032779 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshida, S, Shi, Y , Yanagisawa, M & Togawa, N 2015, An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. in 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February edn, 7032779, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 300-303, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki Island, Okinawa, Japan, 14/11/17. https://doi.org/10.1109/APCCAS.2014.7032779

Yoshida S, Shi Y , Yanagisawa M , Togawa N. An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 300-303. 7032779. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; February). doi: 10.1109/APCCAS.2014.7032779

Yoshida, Shinnosuke ; Shi, Youhua ; Yanagisawa, Masao et al. / An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 300-303 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; February).

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abstract = "As process technologies advance, the importance of timing error correction techniques is increasing as well. In this paper, We propose an area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction circuits (STEPCs). STEPC predicts timing errors by monitoring the middle points of several speed-paths in a circuit. However, we need many STEPCs with a high area overhead to predict timing errors in an overall circuit. Our proposed method moves the STEPC insertion positions to minimize the number of inserted STEPCs. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs. Our proposed algorithm reduces the required number of STEPCs to 1/19 and their area to 1/5 compared with a naive algorithm. Furthermore, our algorithm realizes 2.25X overclocking compared with just inserting STEPCs into several speed-paths.",

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AB - As process technologies advance, the importance of timing error correction techniques is increasing as well. In this paper, We propose an area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction circuits (STEPCs). STEPC predicts timing errors by monitoring the middle points of several speed-paths in a circuit. However, we need many STEPCs with a high area overhead to predict timing errors in an overall circuit. Our proposed method moves the STEPC insertion positions to minimize the number of inserted STEPCs. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs. Our proposed algorithm reduces the required number of STEPCs to 1/19 and their area to 1/5 compared with a naive algorithm. Furthermore, our algorithm realizes 2.25X overclocking compared with just inserting STEPCs into several speed-paths.

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An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

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