An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications

Leona Okamura; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto; Tsutomu Yoshihara

doi:10.1109/ISCIT.2006.339845

An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications

Leona Okamura^*, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

Original language	English
Title of host publication	2006 International Symposium on Communications and Information Technologies, ISCIT
Pages	771-774
Number of pages	4
DOIs	https://doi.org/10.1109/ISCIT.2006.339845
Publication status	Published - 2006
Event	2006 International Symposium on Communications and Information Technologies, ISCIT - Bangkok Duration: 2006 Oct 18 → 2006 Oct 20

Other

Other	2006 International Symposium on Communications and Information Technologies, ISCIT
City	Bangkok
Period	06/10/18 → 06/10/20

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCIT.2006.339845

Cite this

An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications. / Okamura, Leona; Morishita, Fukashi; Dosaka, Katsumi et al.
2006 International Symposium on Communications and Information Technologies, ISCIT. 2006. p. 771-774 4141490.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okamura, L, Morishita, F, Dosaka, K, Arimoto, K & Yoshihara, T 2006, An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications. in 2006 International Symposium on Communications and Information Technologies, ISCIT., 4141490, pp. 771-774, 2006 International Symposium on Communications and Information Technologies, ISCIT, Bangkok, 06/10/18. https://doi.org/10.1109/ISCIT.2006.339845

@inproceedings{39489430f11748eeaccd749107a10c28,

title = "An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications",

abstract = "SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.",

author = "Leona Okamura and Fukashi Morishita and Katsumi Dosaka and Kazutami Arimoto and Tsutomu Yoshihara",

year = "2006",

doi = "10.1109/ISCIT.2006.339845",

language = "English",

pages = "771--774",

booktitle = "2006 International Symposium on Communications and Information Technologies, ISCIT",

note = "2006 International Symposium on Communications and Information Technologies, ISCIT ; Conference date: 18-10-2006 Through 20-10-2006",

}

TY - GEN

T1 - An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications

AU - Okamura, Leona

AU - Morishita, Fukashi

AU - Dosaka, Katsumi

AU - Arimoto, Kazutami

AU - Yoshihara, Tsutomu

PY - 2006

Y1 - 2006

N2 - SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

AB - SOI device has the better potential of high speed, low operating voltage and RF functions like as mobile and wireless network applications. Gate Body directly connected SOI MOSFET without historical effects is one of the promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

UR - http://www.scopus.com/inward/record.url?scp=50949128553&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50949128553&partnerID=8YFLogxK

U2 - 10.1109/ISCIT.2006.339845

DO - 10.1109/ISCIT.2006.339845

M3 - Conference contribution

AN - SCOPUS:50949128553

SP - 771

EP - 774

BT - 2006 International Symposium on Communications and Information Technologies, ISCIT

T2 - 2006 International Symposium on Communications and Information Technologies, ISCIT

Y2 - 18 October 2006 through 20 October 2006

ER -

An automatic source/body level controllable 0.5V level SOI circuit technique for mobile and wireless network applications

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this