Abstract
Network-on-Chips (NoC) has been proven as a flexible solution for Chip-Multiprocessor (CMP) systems due to its reusability and scalability. To increase communication efficiency, Three-Dimensional Networks-on-Chips (3D NoCs) are developed, which can shorten the wire length and improve the system performance. In this paper, we present a novel deadlock-free adaptive routing algorithm for 3D mesh NoC interconnections. The routing rules of traditional XY routing and YX routing are relaxed and used for intra-layer routing. Via multiple layers, balanced adaptiveness can be achieved. We detail the basic principle of this method and test its efficiency through simulations.
| Original language | English |
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| Title of host publication | Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 29-36 |
| Number of pages | 8 |
| Volume | 2018-January |
| ISBN (Electronic) | 9781538634417 |
| DOIs | |
| Publication status | Published - 2018 Mar 26 |
| Event | 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 - Seoul, Korea, Republic of Duration: 2017 Sept 18 → 2017 Sept 20 |
Other
| Other | 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 |
|---|---|
| Country/Territory | Korea, Republic of |
| City | Seoul |
| Period | 17/9/18 → 17/9/20 |
Keywords
- 3D network-on-chip
- adaptive routing
- computer architecture
- multiprocessing systems
ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Hardware and Architecture
- Signal Processing