An efficient hardware routing algorithms for NoC

Yiping Dong*, Zhen Lin, Takahiro Watanabe

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


Networks on Chip (NoC) has been widely discussed for its smart structure and high performance. Routing algorithms significantly influence design cost and system performance of NoC. In this paper, a new hardware method called FinalDestination-Tag (FDT) is proposed to improve the original Destination-Tag (DT) method for implementing different routing algorithms. Compared with the DT method, the proposed FDT method could reduce the header size of the packet. We evaluate NoC with this proposed method in terms of circuit resource, average latency, max latency, average throughput and power consumption. The results indicate that the proposed method is effective in increasing throughput and reducing circuit resource, latency and power consumption for NoC.

Original languageEnglish
Title of host publicationTENCON 2010 - 2010 IEEE Region 10 Conference
Number of pages6
Publication statusPublished - 2010 Dec 1
Event2010 IEEE Region 10 Conference, TENCON 2010 - Fukuoka, Japan
Duration: 2010 Nov 212010 Nov 24

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON


Other2010 IEEE Region 10 Conference, TENCON 2010

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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