An Experimental 4-Mbit CMOS DRAM

Tohru Furuyama; Takashi Ohsawa; Yohji Watanabe; Hidemi Ishiuchi; Toshiharu Watanabe; Takeshi Tanaka; Kenji Natori; Osamu Ozawa

doi:10.1109/JSSC.1986.1052584

An Experimental 4-Mbit CMOS DRAM

Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Hidemi Ishiuchi, Toshiharu Watanabe, Takeshi Tanaka, Kenji Natori, Osamu Ozawa

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

Original language	English
Pages (from-to)	605-611
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	21
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1986.1052584
Publication status	Published - 1986 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1986.1052584

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title = "An Experimental 4-Mbit CMOS DRAM",

abstract = "A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.",

author = "Tohru Furuyama and Takashi Ohsawa and Yohji Watanabe and Hidemi Ishiuchi and Toshiharu Watanabe and Takeshi Tanaka and Kenji Natori and Osamu Ozawa",

year = "1986",

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AU - Furuyama, Tohru

AU - Ohsawa, Takashi

AU - Watanabe, Yohji

AU - Ishiuchi, Hidemi

AU - Watanabe, Toshiharu

AU - Tanaka, Takeshi

AU - Natori, Kenji

AU - Ozawa, Osamu

PY - 1986/10

Y1 - 1986/10

N2 - A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

AB - A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

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An Experimental 4-Mbit CMOS DRAM

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