An FPGA implementation method based on distributed-register architectures

Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa

doi:10.2197/ipsjtsldm.12.38

An FPGA implementation method based on distributed-register architectures

Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

School of Fundamental Science and Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.

Original language	English
Pages (from-to)	38-41
Number of pages	4
Journal	IPSJ Transactions on System LSI Design Methodology
Volume	12
DOIs	https://doi.org/10.2197/ipsjtsldm.12.38
Publication status	Published - 2019 Feb

Keywords

Distributed-register architecture
FPGA implementation
High-level synthesis
Interconnection delay

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

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10.2197/ipsjtsldm.12.38

Cite this

@article{f4fcc0a55e5043dd846ad58ab8fdf47f,

title = "An FPGA implementation method based on distributed-register architectures",

abstract = "In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.",

keywords = "Distributed-register architecture, FPGA implementation, High-level synthesis, Interconnection delay",

author = "Koichi Fujiwara and Kazushi Kawamura and Masao Yanagisawa and Nozomu Togawa",

year = "2019",

month = feb,

doi = "10.2197/ipsjtsldm.12.38",

language = "English",

volume = "12",

pages = "38--41",

journal = "IPSJ Transactions on System LSI Design Methodology",

issn = "1882-6687",

publisher = "Information Processing Society of Japan",

}

TY - JOUR

T1 - An FPGA implementation method based on distributed-register architectures

AU - Fujiwara, Koichi

AU - Kawamura, Kazushi

AU - Yanagisawa, Masao

AU - Togawa, Nozomu

PY - 2019/2

Y1 - 2019/2

N2 - In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.

AB - In order to reduce the effects of interconnection delays in recent FPGA chips, circuit designs based on distributed-register architectures (which we call DR-based circuit designs) are important. Several methods for DR-based circuit designs have been proposed, where high-level synthesis techniques are effectively utilized. However, no methods have been proposed yet to practically implement DR-based circuits on FPGA chips. In this paper, we propose an FPGA implementation method based on DR architectures and apply it to a DR-based circuit. The implementation result shows that it operates on an FPGA chip with 21% faster than the circuit based on a traditional architecture.

KW - Distributed-register architecture

KW - FPGA implementation

KW - High-level synthesis

KW - Interconnection delay

UR - http://www.scopus.com/inward/record.url?scp=85063475371&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85063475371&partnerID=8YFLogxK

U2 - 10.2197/ipsjtsldm.12.38

DO - 10.2197/ipsjtsldm.12.38

M3 - Article

AN - SCOPUS:85063475371

SN - 1882-6687

VL - 12

SP - 38

EP - 41

JO - IPSJ Transactions on System LSI Design Methodology

JF - IPSJ Transactions on System LSI Design Methodology

ER -

An FPGA implementation method based on distributed-register architectures

Abstract

Keywords

ASJC Scopus subject areas

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