An input buffer‐type ATM switching system using schedule comparison

Ruixue Fan*, Minoru Akiyama, Yoshiaki Tanaka

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


An input buffer‐type, high‐capacity ATM switching system using schedule comparison is proposed for a high‐speed ATM switching system whose internal link speed is equal to trunk speed. Its throughput, delay, and loss characteristics are evaluated. The schedule of the input buffer to send cells and that of the output to receive cells are compared to decide the timing to send a cell so that there exists only one cell bound for the same output line. The maximum throughput (outgoing trunk efficiency) is more than 0.9, and the mean delay is less than 10 cell times. Moreover, if a doubled transfer network is used, higher throughput can be achieved and the delay characteristic is almost equal to that with an ideal output buffer type. A comparison of the proposed scheme with the output buffer‐type system under the same cell loss probability 10−5 reveals that the delay is almost the same and the required buffer size is one‐third. This characteristic holds even if the system size is extended to 4096 lines; hence, a super high‐capacity, high‐speed switching system can be configured with the proposed system.

Original languageEnglish
Pages (from-to)17-25
Number of pages9
JournalElectronics and Communications in Japan (Part I: Communications)
Issue number11
Publication statusPublished - 1991 Nov
Externally publishedYes

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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