An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

Shin Ichiro Kimura; Yoshifumi Kawamoto; Norio Hasegawa; Atsushi Hiraiwa; Yoshinobu Nakagome; Masakazu Aoki; Hideo Sunami; Kiyoo Itoh; Teruaki Kisu

doi:10.1109/16.7358

An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

Shin Ichiro Kimura, Yoshifumi Kawamoto, Norio Hasegawa, Atsushi Hiraiwa, Yoshinobu Nakagome, Masakazu Aoki, Hideo Sunami, Kiyoo Itoh, Teruaki Kisu

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.

Original language	English
Pages (from-to)	1591-1595
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	35
Issue number	10
DOIs	https://doi.org/10.1109/16.7358
Publication status	Published - 1988
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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abstract = "A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM{\textquoteright}s.",

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T1 - An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

AU - Kimura, Shin Ichiro

AU - Kawamoto, Yoshifumi

AU - Hasegawa, Norio

AU - Hiraiwa, Atsushi

AU - Nakagome, Yoshinobu

AU - Aoki, Masakazu

AU - Sunami, Hideo

AU - Itoh, Kiyoo

AU - Kisu, Teruaki

PY - 1988

Y1 - 1988

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AB - A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.

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An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

Abstract

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