TY - GEN
T1 - An universal logic-circuit with flip flop circuit based on DG-CNTFET
AU - Miura, Yasuyuki
AU - Ninomiya, Hiroshi
AU - Kobayashi, Manabu
AU - Watanabe, Shigeyoshi
PY - 2013
Y1 - 2013
N2 - In this paper, we propose the method for embedding the latch and the flip flop (FF) circuit to the universal logic circuit of Double Gate Carbon NanoTube Field Effect Transistor (DG-CNTFET) proposed in the previous work. Previously, 2-inputs universal logic circuit by 8 DG-CNTFET was proposed. If the embedding of flip flop to them is possible, the reconfigurable circuit which includes a state such as flip flop can be realized. The result of our research shows that SR-latch and D-latch with 3-inputs/state can be embedded within 2-inputs universal logic circuit. Thus it is shown that a D-FF can be embedded to two 2-inputs universal logic circuit.
AB - In this paper, we propose the method for embedding the latch and the flip flop (FF) circuit to the universal logic circuit of Double Gate Carbon NanoTube Field Effect Transistor (DG-CNTFET) proposed in the previous work. Previously, 2-inputs universal logic circuit by 8 DG-CNTFET was proposed. If the embedding of flip flop to them is possible, the reconfigurable circuit which includes a state such as flip flop can be realized. The result of our research shows that SR-latch and D-latch with 3-inputs/state can be embedded within 2-inputs universal logic circuit. Thus it is shown that a D-FF can be embedded to two 2-inputs universal logic circuit.
KW - Ambipolar device
KW - Binary decision diagram
KW - Double gate CNTFET
KW - Reconfigarable logic design
UR - http://www.scopus.com/inward/record.url?scp=84889038186&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84889038186&partnerID=8YFLogxK
U2 - 10.1109/PACRIM.2013.6625465
DO - 10.1109/PACRIM.2013.6625465
M3 - Conference contribution
AN - SCOPUS:84889038186
SN - 9781479915019
T3 - IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings
SP - 148
EP - 152
BT - 2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2013
T2 - 14th IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, PACRIM 2013
Y2 - 27 August 2013 through 29 August 2013
ER -