Analysis of parasitic resistance effects in MOS LSI

Kenji Anami*, Masahiko Yoshimoto, Hirofumi Shinohara, Osamu Tomisawa, Takao Nakano

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This paper describes simplified analysis of the effects of transistor source and drain parasitic resistances and interconnect resistance in MOS LSI's, and their application to the circuit designs for MOS LSI circuits and mask patterns. Heretofore the analysis of parasitic resistance effects has been complex and could only be calculated numerically with circuit analysis programs. However, in this paper, a simple expression is given for the effect of the source and drain parasitic resistances by using a linear approximation to the MOS transistor drain i‐v characteristics. Furthermore, the delays caused by interconnection resistance are analyzed under assumptions that are actually obtained in practical LSI's. the rules for optimum design of the crossunders used frequently in LSI's are obtained using the result. Finally, experimental results from MOS transistors which agreed well with the source and drain parasitic resistance effect analysis. A ring oscillator experiment which also resulted in good agreement with the interconnect resistance delay analysis shows the applicability of both analysis methods.

Original languageEnglish
Pages (from-to)106-113
Number of pages8
JournalElectronics and Communications in Japan (Part I: Communications)
Issue number10
Publication statusPublished - 1983
Externally publishedYes

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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