Analytical model of static noise margin in CMOS SRAM for variation consideration

Hirofumi Shinohara*, Koji Nii, Hidetoshi Onodera

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

Original languageEnglish
Pages (from-to)1488-1500
Number of pages13
JournalIEICE Transactions on Electronics
Issue number9
Publication statusPublished - 2008 Sept
Externally publishedYes


  • Memory cell
  • SNM
  • SRAM
  • Static noise margin
  • Variability

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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