Analytical model of static noise margin in CMOS SRAM for variation consideration

Hirofumi Shinohara; Koji Nii; Hidetoshi Onodera

doi:10.1093/ietele/e91-c.9.1488

Analytical model of static noise margin in CMOS SRAM for variation consideration

Hirofumi Shinohara^*, Koji Nii, Hidetoshi Onodera

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random V_th variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low V_DD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as V_th, the W ratio, and V_DD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

Original language	English
Pages (from-to)	1488-1500
Number of pages	13
Journal	IEICE Transactions on Electronics
Volume	E91-C
Issue number	9
DOIs	https://doi.org/10.1093/ietele/e91-c.9.1488
Publication status	Published - 2008 Sept
Externally published	Yes

Keywords

Memory cell
SNM
SRAM
Static noise margin
Variability

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1093/ietele/e91-c.9.1488

Cite this

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title = "Analytical model of static noise margin in CMOS SRAM for variation consideration",

abstract = "An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.",

keywords = "Memory cell, SNM, SRAM, Static noise margin, Variability",

author = "Hirofumi Shinohara and Koji Nii and Hidetoshi Onodera",

year = "2008",

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doi = "10.1093/ietele/e91-c.9.1488",

language = "English",

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TY - JOUR

T1 - Analytical model of static noise margin in CMOS SRAM for variation consideration

AU - Shinohara, Hirofumi

AU - Nii, Koji

AU - Onodera, Hidetoshi

PY - 2008/9

Y1 - 2008/9

N2 - An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

AB - An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

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KW - SRAM

KW - Static noise margin

KW - Variability

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Analytical model of static noise margin in CMOS SRAM for variation consideration

Abstract

Keywords

ASJC Scopus subject areas

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