Approaches to extra low voltage dram operation by soi-dram

Takahisa Eimori; Toshiyuki Oashi; Fukashi Morishita; Toshiaki Iwamatsu; Yasuo Yamaguchi; Fumihiro Okuda; Ke N.Ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Kazutami Arimoto; Yasuo Inoue; Shinji Komori; Masahide Inuishi; Tadashi Nishimura; Hirokazu Miyoshi

doi:10.1109/16.669509

Approaches to extra low voltage dram operation by soi-dram

Takahisa Eimori^*, Toshiyuki Oashi, Fukashi Morishita, Toshiaki Iwamatsu, Yasuo Yamaguchi, Fumihiro Okuda, Ke N.Ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Kazutami Arimoto, Yasuo Inoue, Shinji Komori, Masahide Inuishi, Tadashi Nishimura, Hirokazu Miyoshi

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFET's with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFET's to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

Original language	English
Pages (from-to)	1000-1009
Number of pages	10
Journal	IEEE Transactions on Electron Devices
Volume	45
Issue number	5
DOIs	https://doi.org/10.1109/16.669509
Publication status	Published - 1998
Externally published	Yes

Keywords

DRAM
High-speed circuits/devices
Silicon-oninsulator

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/16.669509

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@article{9ed25a859ad442feb81ef29e8afdfa7f,

title = "Approaches to extra low voltage dram operation by soi-dram",

abstract = "The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFET's with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFET's to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.",

keywords = "DRAM, High-speed circuits/devices, Silicon-oninsulator",

author = "Takahisa Eimori and Toshiyuki Oashi and Fukashi Morishita and Toshiaki Iwamatsu and Yasuo Yamaguchi and Fumihiro Okuda and Shimomura, {Ke N.Ichi} and Hiroki Shimano and Narumi Sakashita and Kazutami Arimoto and Yasuo Inoue and Shinji Komori and Masahide Inuishi and Tadashi Nishimura and Hirokazu Miyoshi",

year = "1998",

doi = "10.1109/16.669509",

language = "English",

volume = "45",

pages = "1000--1009",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Approaches to extra low voltage dram operation by soi-dram

AU - Eimori, Takahisa

AU - Oashi, Toshiyuki

AU - Morishita, Fukashi

AU - Iwamatsu, Toshiaki

AU - Yamaguchi, Yasuo

AU - Okuda, Fumihiro

AU - Shimomura, Ke N.Ichi

AU - Shimano, Hiroki

AU - Sakashita, Narumi

AU - Arimoto, Kazutami

AU - Inoue, Yasuo

AU - Komori, Shinji

AU - Inuishi, Masahide

AU - Nishimura, Tadashi

AU - Miyoshi, Hirokazu

PY - 1998

Y1 - 1998

N2 - The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFET's with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFET's to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

AB - The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFET's with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFET's to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

KW - DRAM

KW - High-speed circuits/devices

KW - Silicon-oninsulator

UR - http://www.scopus.com/inward/record.url?scp=0032075636&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032075636&partnerID=8YFLogxK

U2 - 10.1109/16.669509

DO - 10.1109/16.669509

M3 - Article

AN - SCOPUS:0032075636

SN - 0018-9383

VL - 45

SP - 1000

EP - 1009

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 5

ER -

Approaches to extra low voltage dram operation by soi-dram

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Keywords

ASJC Scopus subject areas

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