Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

Katsuyuki Fujita; Takashi Ohsawa; Ryo Fukuda; Fumiyoshi Matsuoka; Tomoki Higashi; Tomoaki Shino; Yohji Watanabe

doi:10.1109/SOI.2008.4656280

Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

Katsuyuki Fujita^*, Takashi Ohsawa, Ryo Fukuda, Fumiyoshi Matsuoka, Tomoki Higashi, Tomoaki Shino, Yohji Watanabe

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.

Original language	English
Title of host publication	2008 IEEE International SOI Conference Proceedings
Pages	31-32
Number of pages	2
DOIs	https://doi.org/10.1109/SOI.2008.4656280
Publication status	Published - 2008 Dec 24
Externally published	Yes
Event	2008 IEEE International SOI Conference - New Paltz, NY, United States Duration: 2008 Oct 6 → 2008 Oct 9

Publication series

Name	Proceedings - IEEE International SOI Conference
ISSN (Print)	1078-621X

Other

Other	2008 IEEE International SOI Conference
Country/Territory	United States
City	New Paltz, NY
Period	08/10/6 → 08/10/9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/SOI.2008.4656280

Cite this

Fujita, K., Ohsawa, T., Fukuda, R., Matsuoka, F., Higashi, T., Shino, T., & Watanabe, Y. (2008). Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node. In 2008 IEEE International SOI Conference Proceedings (pp. 31-32). Article 4656280 (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2008.4656280

Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node. / Fujita, Katsuyuki; Ohsawa, Takashi; Fukuda, Ryo et al.
2008 IEEE International SOI Conference Proceedings. 2008. p. 31-32 4656280 (Proceedings - IEEE International SOI Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujita, K, Ohsawa, T, Fukuda, R, Matsuoka, F, Higashi, T, Shino, T & Watanabe, Y 2008, Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node. in 2008 IEEE International SOI Conference Proceedings., 4656280, Proceedings - IEEE International SOI Conference, pp. 31-32, 2008 IEEE International SOI Conference, New Paltz, NY, United States, 08/10/6. https://doi.org/10.1109/SOI.2008.4656280

@inproceedings{dfc6b6cc5d154b529836165bd6f6c663,

title = "Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node",

abstract = "Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.",

author = "Katsuyuki Fujita and Takashi Ohsawa and Ryo Fukuda and Fumiyoshi Matsuoka and Tomoki Higashi and Tomoaki Shino and Yohji Watanabe",

year = "2008",

month = dec,

day = "24",

doi = "10.1109/SOI.2008.4656280",

language = "English",

isbn = "9781424419548",

series = "Proceedings - IEEE International SOI Conference",

pages = "31--32",

booktitle = "2008 IEEE International SOI Conference Proceedings",

note = "2008 IEEE International SOI Conference ; Conference date: 06-10-2008 Through 09-10-2008",

}

TY - GEN

T1 - Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

AU - Fujita, Katsuyuki

AU - Ohsawa, Takashi

AU - Fukuda, Ryo

AU - Matsuoka, Fumiyoshi

AU - Higashi, Tomoki

AU - Shino, Tomoaki

AU - Watanabe, Yohji

PY - 2008/12/24

Y1 - 2008/12/24

N2 - Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.

AB - Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.

UR - http://www.scopus.com/inward/record.url?scp=57749197395&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=57749197395&partnerID=8YFLogxK

U2 - 10.1109/SOI.2008.4656280

DO - 10.1109/SOI.2008.4656280

M3 - Conference contribution

AN - SCOPUS:57749197395

SN - 9781424419548

T3 - Proceedings - IEEE International SOI Conference

SP - 31

EP - 32

BT - 2008 IEEE International SOI Conference Proceedings

T2 - 2008 IEEE International SOI Conference

Y2 - 6 October 2008 through 9 October 2008

ER -

Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

Abstract

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ASJC Scopus subject areas

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