At-speed testing with timing exceptions and constraints -case studies

Dhiraj Goswami*, Kun Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)


In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in [1][2]. The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism.

Original languageEnglish
Title of host publicationProceedings of the 15th Asian Test Symposium 2006
Number of pages7
Publication statusPublished - 2006
Externally publishedYes
Event15th Asian Test Symposium 2006 - Fukuoka, Japan
Duration: 2006 Nov 202006 Nov 23

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference15th Asian Test Symposium 2006


  • At-speed test
  • False paths
  • Multicycle paths
  • Static timing analysis (STA)
  • Synopsys design constraints (SDC)
  • Timing constraints
  • Timing exceptions

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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