AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS.

M. Ishikawa; T. Matsuda; Takeshi Yoshimura; S. Goto

AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS.

M. Ishikawa^*, T. Matsuda, Takeshi Yoshimura, S. Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The authors propose an automatic compaction method which minimizes the layout area for building block LSIs. A feature of this method is automatic wiring bend 'jog' insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that this method compresses the layout area to an amount only 1. 2-1. 5 times larger than that resulting from manual layout and therefore is very effective for achieving a minimum chip layout design. 8 refs.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	203-206
Number of pages	4
Publication status	Published - 1985
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

@inproceedings{1cee96e353f14a1492562a24f35ce381,

title = "AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS.",

abstract = "The authors propose an automatic compaction method which minimizes the layout area for building block LSIs. A feature of this method is automatic wiring bend 'jog' insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that this method compresses the layout area to an amount only 1. 2-1. 5 times larger than that resulting from manual layout and therefore is very effective for achieving a minimum chip layout design. 8 refs.",

author = "M. Ishikawa and T. Matsuda and Takeshi Yoshimura and S. Goto",

year = "1985",

language = "English",

pages = "203--206",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

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TY - GEN

T1 - AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS.

AU - Ishikawa, M.

AU - Matsuda, T.

AU - Yoshimura, Takeshi

AU - Goto, S.

PY - 1985

Y1 - 1985

N2 - The authors propose an automatic compaction method which minimizes the layout area for building block LSIs. A feature of this method is automatic wiring bend 'jog' insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that this method compresses the layout area to an amount only 1. 2-1. 5 times larger than that resulting from manual layout and therefore is very effective for achieving a minimum chip layout design. 8 refs.

AB - The authors propose an automatic compaction method which minimizes the layout area for building block LSIs. A feature of this method is automatic wiring bend 'jog' insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that this method compresses the layout area to an amount only 1. 2-1. 5 times larger than that resulting from manual layout and therefore is very effective for achieving a minimum chip layout design. 8 refs.

UR - http://www.scopus.com/inward/record.url?scp=0022320421&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022320421&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0022320421

SP - 203

EP - 206

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -

AUTOMATIC COMPACTION METHOD FOR BUILDING BLOCK LSIS.

Abstract

ASJC Scopus subject areas

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