Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Nobuhiro Doi; Takashi Horiyama; Masaki Nakanishi; Shinji Kimura; Katsumasa Watanabe

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Nobuhiro Doi^*, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.

Original language	English
Pages (from-to)	3184-3191
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E86-A
Issue number	12
Publication status	Published - 2003 Dec

Keywords

Bit length
HDL
High-level synthesis
Parallelizing compiler

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Cite this

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis. / Doi, Nobuhiro; Horiyama, Takashi; Nakanishi, Masaki et al.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 12, 12.2003, p. 3184-3191.

Research output: Contribution to journal › Article › peer-review

@article{f57a9c8e8d3d4237a0d6b8305ca75775,

title = "Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis",

abstract = "In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.",

keywords = "Bit length, HDL, High-level synthesis, Parallelizing compiler",

author = "Nobuhiro Doi and Takashi Horiyama and Masaki Nakanishi and Shinji Kimura and Katsumasa Watanabe",

year = "2003",

month = dec,

language = "English",

volume = "E86-A",

pages = "3184--3191",

journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",

issn = "0916-8508",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "12",

}

TY - JOUR

T1 - Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

AU - Doi, Nobuhiro

AU - Horiyama, Takashi

AU - Nakanishi, Masaki

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 2003/12

Y1 - 2003/12

N2 - In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.

AB - In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.

KW - Bit length

KW - HDL

KW - High-level synthesis

KW - Parallelizing compiler

UR - http://www.scopus.com/inward/record.url?scp=0842332224&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0842332224&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0842332224

SN - 0916-8508

VL - E86-A

SP - 3184

EP - 3191

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IS - 12

ER -

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

Abstract

Keywords

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this