Body bias controlled SOI technology with HTI

Mikio Tsujiuchi; Yuuichi Hirano; Toshiaki Iwamatsu; Takashi Ipposhi; Shigeto Maegawa; Masahide Inuishi; Yuzuru Ohji

doi:10.1109/IMFEDK.2004.1566443

Body bias controlled SOI technology with HTI

Mikio Tsujiuchi, Yuuichi Hirano, Toshiaki Iwamatsu, Takashi Ipposhi, Shigeto Maegawa, Masahide Inuishi, Yuzuru Ohji

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn't need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.

Original language	English
Title of host publication	IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	131-132
Number of pages	2
ISBN (Electronic)	0780384237, 9780780384231
DOIs	https://doi.org/10.1109/IMFEDK.2004.1566443
Publication status	Published - 2004
Externally published	Yes
Event	2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004 - Kyoto, Japan Duration: 2004 Jul 26 → 2004 Jul 28

Other

Other	2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004
Country/Territory	Japan
City	Kyoto
Period	04/7/26 → 04/7/28

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/IMFEDK.2004.1566443

Cite this

Tsujiuchi, M, Hirano, Y, Iwamatsu, T, Ipposhi, T, Maegawa, S, Inuishi, M & Ohji, Y 2004, Body bias controlled SOI technology with HTI. in IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai., 1566443, Institute of Electrical and Electronics Engineers Inc., pp. 131-132, 2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004, Kyoto, Japan, 04/7/26. https://doi.org/10.1109/IMFEDK.2004.1566443

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title = "Body bias controlled SOI technology with HTI",

abstract = "As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn't need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.",

author = "Mikio Tsujiuchi and Yuuichi Hirano and Toshiaki Iwamatsu and Takashi Ipposhi and Shigeto Maegawa and Masahide Inuishi and Yuzuru Ohji",

year = "2004",

doi = "10.1109/IMFEDK.2004.1566443",

language = "English",

pages = "131--132",

booktitle = "IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004 ; Conference date: 26-07-2004 Through 28-07-2004",

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T1 - Body bias controlled SOI technology with HTI

AU - Tsujiuchi, Mikio

AU - Hirano, Yuuichi

AU - Iwamatsu, Toshiaki

AU - Ipposhi, Takashi

AU - Maegawa, Shigeto

AU - Inuishi, Masahide

AU - Ohji, Yuzuru

PY - 2004

Y1 - 2004

N2 - As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn't need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.

AB - As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn't need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.

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SP - 131

EP - 132

BT - IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004

Y2 - 26 July 2004 through 28 July 2004

ER -

Body bias controlled SOI technology with HTI

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