Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

Xiao Xu; Xin Yang; Taufiq Alif Kurniawan; Toshihiko Yoshimasu

doi:10.1109/EDSSC.2015.7285200

Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

Xiao Xu, Xin Yang, Taufiq Alif Kurniawan, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

Original language	English
Title of host publication	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	653-655
Number of pages	3
ISBN (Print)	9781479983636
DOIs	https://doi.org/10.1109/EDSSC.2015.7285200
Publication status	Published - 2015 Sept 30
Event	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore Duration: 2015 Jun 1 → 2015 Jun 4

Other

Other	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Country/Territory	Singapore
City	Singapore
Period	15/6/1 → 15/6/4

Keywords

floating body technique
high isolation
SPDT switch IC
stacked transistor
wideband

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2015.7285200

Cite this

Xu, X., Yang, X., Kurniawan, T. A., & Yoshimasu, T. (2015). Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 653-655). [7285200] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285200

Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. / Xu, Xiao; Yang, Xin; Kurniawan, Taufiq Alif et al.
Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 653-655 7285200.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Xu, X, Yang, X, Kurniawan, TA & Yoshimasu, T 2015, Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. in Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015., 7285200, Institute of Electrical and Electronics Engineers Inc., pp. 653-655, 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Singapore, Singapore, 15/6/1. https://doi.org/10.1109/EDSSC.2015.7285200

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title = "Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS",

abstract = "This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.",

keywords = "floating body technique, high isolation, SPDT switch IC, stacked transistor, wideband",

author = "Xiao Xu and Xin Yang and Kurniawan, {Taufiq Alif} and Toshihiko Yoshimasu",

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doi = "10.1109/EDSSC.2015.7285200",

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N2 - This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

AB - This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

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KW - wideband

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Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

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Keywords

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