Cache miss reduction through hardware-assisted loop optimization

Kang Zhao; Jinian Bian; Chenqian Jiang; Sheqin Dong; Satoshi Goto

doi:10.1109/CSCWD.2008.4536969

Cache miss reduction through hardware-assisted loop optimization

Kang Zhao^*, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

Original language	English
Title of host publication	Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD
Pages	129-134
Number of pages	6
Volume	1
DOIs	https://doi.org/10.1109/CSCWD.2008.4536969
Publication status	Published - 2008
Event	2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD - Xi'an Duration: 2008 Apr 16 → 2008 Apr 18

Other

Other	2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD
City	Xi'an
Period	08/4/16 → 08/4/18

Keywords

ASIP
Cache miss
CSCW design
Hardware/software co-design

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Human-Computer Interaction

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10.1109/CSCWD.2008.4536969

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Zhao, K, Bian, J, Jiang, C, Dong, S & Goto, S 2008, Cache miss reduction through hardware-assisted loop optimization. in Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD. vol. 1, 4536969, pp. 129-134, 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD, Xi'an, 08/4/16. https://doi.org/10.1109/CSCWD.2008.4536969

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abstract = "To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.",

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AU - Bian, Jinian

AU - Jiang, Chenqian

AU - Dong, Sheqin

AU - Goto, Satoshi

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Y1 - 2008

N2 - To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

AB - To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

KW - ASIP

KW - Cache miss

KW - CSCW design

KW - Hardware/software co-design

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ER -

Cache miss reduction through hardware-assisted loop optimization

Abstract

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Keywords

ASJC Scopus subject areas

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