Calculating the effective capacitance for interconnect loads based on thevenin model

Shuai Fang; Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue

doi:10.1109/ICCCAS.2006.285176

Calculating the effective capacitance for interconnect loads based on thevenin model

Shuai Fang^*, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance C_eff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C _eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

Original language	English
Title of host publication	2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
Pages	2474-2477
Number of pages	4
Volume	4
DOIs	https://doi.org/10.1109/ICCCAS.2006.285176
Publication status	Published - 2006
Event	2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin Duration: 2006 Jun 25 → 2006 Jun 28

Other

Other	2006 International Conference on Communications, Circuits and Systems, ICCCAS
City	Guilin
Period	06/6/25 → 06/6/28

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ICCCAS.2006.285176

Cite this

Fang, S, Huang, Z, Kurokawa, A & Inoue, Y 2006, Calculating the effective capacitance for interconnect loads based on thevenin model. in 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings. vol. 4, 4064423, pp. 2474-2477, 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Guilin, 06/6/25. https://doi.org/10.1109/ICCCAS.2006.285176

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title = "Calculating the effective capacitance for interconnect loads based on thevenin model",

abstract = "Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.",

author = "Shuai Fang and Zhangcai Huang and Atsushi Kurokawa and Yasuaki Inoue",

year = "2006",

doi = "10.1109/ICCCAS.2006.285176",

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volume = "4",

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note = "2006 International Conference on Communications, Circuits and Systems, ICCCAS ; Conference date: 25-06-2006 Through 28-06-2006",

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AU - Fang, Shuai

AU - Huang, Zhangcai

AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

PY - 2006

Y1 - 2006

N2 - Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

AB - Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

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DO - 10.1109/ICCCAS.2006.285176

M3 - Conference contribution

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SN - 0780395840

SN - 9780780395848

VL - 4

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BT - 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings

T2 - 2006 International Conference on Communications, Circuits and Systems, ICCCAS

Y2 - 25 June 2006 through 28 June 2006

ER -

Calculating the effective capacitance for interconnect loads based on thevenin model

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