Cell array design with row-driven source line in block shunt architecture applicable to future 6f2 1t1mtj memory

Tongshuang Huang; Takashi Ohsawa

doi:10.1109/VLSI-TSA.2019.8804671

Cell array design with row-driven source line in block shunt architecture applicable to future 6f² 1t1mtj memory

Tongshuang Huang, Takashi Ohsawa

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose a new 1T1MTJ cell array architecture with SL parallel to WL to achieve a small cell size, in which page mode write can be realized without performance degradation. We propose a row-driven source line (RSL) 1T1MTJ memory cell array architecture for minimizing the cell size and a corresponding operational waveform. A block shunt architecture (BSA) that shunts lower source line (LSL) and upper source line (USL) is proposed to make page mode write possible. Size of 1T1MTJ cell can be shrunk to 6F2 when the state-of-The-Art design rules are applied.

Original language	English
Title of host publication	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728109428
DOIs	https://doi.org/10.1109/VLSI-TSA.2019.8804671
Publication status	Published - 2019 Apr
Event	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan, Province of China Duration: 2019 Apr 22 → 2019 Apr 25

Publication series

Name	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	19/4/22 → 19/4/25

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/VLSI-TSA.2019.8804671

Cite this

Huang, T., & Ohsawa, T. (2019). Cell array design with row-driven source line in block shunt architecture applicable to future 6f² 1t1mtj memory. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 Article 8804671 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2019.8804671

Cell array design with row-driven source line in block shunt architecture applicable to future 6f² 1t1mtj memory. / Huang, Tongshuang; Ohsawa, Takashi.
2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8804671 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Huang, T & Ohsawa, T 2019, Cell array design with row-driven source line in block shunt architecture applicable to future 6f² 1t1mtj memory. in 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019., 8804671, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Hsinchu, Taiwan, Province of China, 19/4/22. https://doi.org/10.1109/VLSI-TSA.2019.8804671

Huang T, Ohsawa T. Cell array design with row-driven source line in block shunt architecture applicable to future 6f² 1t1mtj memory. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8804671. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). doi: 10.1109/VLSI-TSA.2019.8804671

Huang, Tongshuang ; Ohsawa, Takashi. / Cell array design with row-driven source line in block shunt architecture applicable to future 6f² 1t1mtj memory. 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

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