Charge sharing clock scheme for high efficiency double charge pump circuit

Mengshu Huang; Leona Okamura; Tsutomu Yoshihara

doi:10.1109/ICSICT.2010.5667772

Charge sharing clock scheme for high efficiency double charge pump circuit

Mengshu Huang^*, Leona Okamura, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps.

Original language	English
Title of host publication	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	248-250
Number of pages	3
DOIs	https://doi.org/10.1109/ICSICT.2010.5667772
Publication status	Published - 2010
Event	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai Duration: 2010 Nov 1 → 2010 Nov 4

Other

Other	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
City	Shanghai
Period	10/11/1 → 10/11/4

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICSICT.2010.5667772

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Huang, M, Okamura, L & Yoshihara, T 2010, Charge sharing clock scheme for high efficiency double charge pump circuit. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667772, pp. 248-250, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, 10/11/1. https://doi.org/10.1109/ICSICT.2010.5667772

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abstract = "A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps.",

author = "Mengshu Huang and Leona Okamura and Tsutomu Yoshihara",

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doi = "10.1109/ICSICT.2010.5667772",

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AU - Huang, Mengshu

AU - Okamura, Leona

AU - Yoshihara, Tsutomu

PY - 2010

Y1 - 2010

N2 - A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps.

AB - A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps.

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BT - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

T2 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

Y2 - 1 November 2010 through 4 November 2010

ER -

Charge sharing clock scheme for high efficiency double charge pump circuit

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