CIRCUIT DESIGN OF DYNAMIC MOS RAM WITH CONSIDERATION OF SOFT ERROR.

Yasuji Nagayama; Masaki Kumanoya; Michihiro Yamada; Tsutomu Yoshihara; Makoto Taniguchi

CIRCUIT DESIGN OF DYNAMIC MOS RAM WITH CONSIDERATION OF SOFT ERROR.

Yasuji Nagayama^*, Masaki Kumanoya, Michihiro Yamada, Tsutomu Yoshihara, Makoto Taniguchi

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high-speed, low soft error rate and low power consumption.

Original language	English
Pages (from-to)	92-101
Number of pages	10
Journal	Electronics & communications in Japan
Volume	65
Issue number	7
Publication status	Published - 1983 Jul
Externally published	Yes

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "CIRCUIT DESIGN OF DYNAMIC MOS RAM WITH CONSIDERATION OF SOFT ERROR.",

abstract = "Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high-speed, low soft error rate and low power consumption.",

author = "Yasuji Nagayama and Masaki Kumanoya and Michihiro Yamada and Tsutomu Yoshihara and Makoto Taniguchi",

year = "1983",

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AU - Nagayama, Yasuji

AU - Kumanoya, Masaki

AU - Yamada, Michihiro

AU - Yoshihara, Tsutomu

AU - Taniguchi, Makoto

PY - 1983/7

Y1 - 1983/7

N2 - Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high-speed, low soft error rate and low power consumption.

AB - Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high-speed, low soft error rate and low power consumption.

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CIRCUIT DESIGN OF DYNAMIC MOS RAM WITH CONSIDERATION OF SOFT ERROR.

Abstract

ASJC Scopus subject areas

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