Circuit partitioning algorithm with replication capability for multi-FPGA systems

Nozomu Togawa; Masao Sato; Tatsuo Ohtsuki

Circuit partitioning algorithm with replication capability for multi-FPGA systems

Nozomu Togawa^*, Masao Sato, Tatsuo Ohtsuki

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

Original language	English
Pages (from-to)	1765-1776
Number of pages	12
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E78-A
Issue number	12
Publication status	Published - 1995 Dec 1

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Cite this

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AB - An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

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Circuit partitioning algorithm with replication capability for multi-FPGA systems

Abstract

ASJC Scopus subject areas

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