Clock skew estimate modeling for FPGA high-level synthesis and its application

Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ASICON.2015.7516905

Clock skew estimate modeling for FPGA high-level synthesis and its application

Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479984831
DOIs	https://doi.org/10.1109/ASICON.2015.7516905
Publication status	Published - 2016 Jul 19
Event	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 2015 Nov 3 → 2015 Nov 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Country/Territory	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASICON.2015.7516905

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Clock skew estimate modeling for FPGA high-level synthesis and its application. / Fujiwara, Koichi; Kawamura, Kazushi; Yanagisawa, Masao et al.
Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7516905.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujiwara, K, Kawamura, K, Yanagisawa, M & Togawa, N 2016, Clock skew estimate modeling for FPGA high-level synthesis and its application. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516905, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516905

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abstract = "Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.",

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Y1 - 2016/7/19

N2 - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

AB - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

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Clock skew estimate modeling for FPGA high-level synthesis and its application

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