Abstract
A design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1. 2-1. 4 times larger than that resulting from manual layouts. It is concluded that this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.
| Original language | English |
|---|---|
| Pages (from-to) | 374-382 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | CAD-6 |
| Issue number | 3 |
| Publication status | Published - 1987 May |
| Externally published | Yes |
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Computer Science Applications
- Hardware and Architecture
- Electrical and Electronic Engineering