Abstract
A new design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that the resulting chip size is only 1. 2-1. 4 times larger than that resulting from manual layout. Therefore, this compaction-based custom LSI layout method is effective for achieving a minimal chip layout design.
| Original language | English |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Place of Publication | New York, NY, USA |
| Publisher | IEEE |
| Pages | 343-345 |
| Number of pages | 3 |
| ISBN (Print) | 0818606878 |
| Publication status | Published - 1985 |
ASJC Scopus subject areas
- Engineering(all)