Comparison of preemption schemes for partially reconfigurable FPGAs

Krzysztof Jozwik*, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Citations (Scopus)


Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization.

Original languageEnglish
Article number6179510
Pages (from-to)45-48
Number of pages4
JournalIEEE Embedded Systems Letters
Issue number2
Publication statusPublished - 2012
Externally publishedYes


  • Dynamic reconfiguration
  • FPGA
  • runtime reconfiguration

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)


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