TY - GEN
T1 - Concurrent faulty clock detection for crypto circuits against clock glitch based DFA
AU - Igarashi, Hiroaki
AU - Shi, Youhua
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2013
Y1 - 2013
N2 - In this paper, a concurrent faulty clock detection method is proposed for crypto circuits against clock glitch based differential fault analysis (DFA). In the proposed method, a nonlogic buffer-based delay chain is inserted, and then by monitoring the delay along the delay chain, a possible clock glitch based DFA can be detected. Experimental results on an AES circuit show that the proposed method can successfully detect clock glitch based attacks, and the required area overhead is only 0.47% that is much smaller than previous works.
AB - In this paper, a concurrent faulty clock detection method is proposed for crypto circuits against clock glitch based differential fault analysis (DFA). In the proposed method, a nonlogic buffer-based delay chain is inserted, and then by monitoring the delay along the delay chain, a possible clock glitch based DFA can be detected. Experimental results on an AES circuit show that the proposed method can successfully detect clock glitch based attacks, and the required area overhead is only 0.47% that is much smaller than previous works.
KW - advanced encryption standard
KW - clock glitch
KW - crypto circuit
KW - differential fault attack
KW - side-channel attacks
UR - http://www.scopus.com/inward/record.url?scp=84883331247&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883331247&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2013.6572125
DO - 10.1109/ISCAS.2013.6572125
M3 - Conference contribution
AN - SCOPUS:84883331247
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1432
EP - 1435
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -