Correlation between static random access memory power-up state and transistor variation

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)


The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply.

Original languageEnglish
Article number04CD03
JournalJapanese journal of applied physics
Issue number4
Publication statusPublished - 2017 Apr

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)


Dive into the research topics of 'Correlation between static random access memory power-up state and transistor variation'. Together they form a unique fingerprint.

Cite this