Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application

Mengshu Huang; Leona Okamura; Tsutomu Yoshihara

doi:10.1109/SOCDC.2010.5682935

Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application

Mengshu Huang^*, Leona Okamura, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A high area efficiency hybrid decoupling scheme using both passive and active capacitors is designed to suppress the program noise of charge pump in non-volatile memory. Through the decoupling impedance analysis and noise power calculation, an optimized ratio between the passive and active capacitors is obtained to achieve maximum noise suppression performance. The proposed hybrid decoupling charge pump is fabricated in 0.18μm technology with 1V supply voltage. The results show a nearly 20dB noise-suppression-ratio (NSR) to the conventional method and the ripple voltage reduction is 73%. The area overhead is only 2%.

Original language	English
Title of host publication	2010 International SoC Design Conference, ISOCC 2010
Pages	205-208
Number of pages	4
DOIs	https://doi.org/10.1109/SOCDC.2010.5682935
Publication status	Published - 2010
Event	2010 International SoC Design Conference, ISOCC 2010 - Incheon Duration: 2010 Nov 22 → 2010 Nov 23

Other

Other	2010 International SoC Design Conference, ISOCC 2010
City	Incheon
Period	10/11/22 → 10/11/23

ASJC Scopus subject areas

Hardware and Architecture

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10.1109/SOCDC.2010.5682935

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title = "Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application",

abstract = "A high area efficiency hybrid decoupling scheme using both passive and active capacitors is designed to suppress the program noise of charge pump in non-volatile memory. Through the decoupling impedance analysis and noise power calculation, an optimized ratio between the passive and active capacitors is obtained to achieve maximum noise suppression performance. The proposed hybrid decoupling charge pump is fabricated in 0.18μm technology with 1V supply voltage. The results show a nearly 20dB noise-suppression-ratio (NSR) to the conventional method and the ripple voltage reduction is 73%. The area overhead is only 2%.",

author = "Mengshu Huang and Leona Okamura and Tsutomu Yoshihara",

year = "2010",

doi = "10.1109/SOCDC.2010.5682935",

language = "English",

isbn = "9781424486335",

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note = "2010 International SoC Design Conference, ISOCC 2010 ; Conference date: 22-11-2010 Through 23-11-2010",

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T1 - Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application

AU - Huang, Mengshu

AU - Okamura, Leona

AU - Yoshihara, Tsutomu

PY - 2010

Y1 - 2010

N2 - A high area efficiency hybrid decoupling scheme using both passive and active capacitors is designed to suppress the program noise of charge pump in non-volatile memory. Through the decoupling impedance analysis and noise power calculation, an optimized ratio between the passive and active capacitors is obtained to achieve maximum noise suppression performance. The proposed hybrid decoupling charge pump is fabricated in 0.18μm technology with 1V supply voltage. The results show a nearly 20dB noise-suppression-ratio (NSR) to the conventional method and the ripple voltage reduction is 73%. The area overhead is only 2%.

AB - A high area efficiency hybrid decoupling scheme using both passive and active capacitors is designed to suppress the program noise of charge pump in non-volatile memory. Through the decoupling impedance analysis and noise power calculation, an optimized ratio between the passive and active capacitors is obtained to achieve maximum noise suppression performance. The proposed hybrid decoupling charge pump is fabricated in 0.18μm technology with 1V supply voltage. The results show a nearly 20dB noise-suppression-ratio (NSR) to the conventional method and the ripple voltage reduction is 73%. The area overhead is only 2%.

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DO - 10.1109/SOCDC.2010.5682935

M3 - Conference contribution

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EP - 208

BT - 2010 International SoC Design Conference, ISOCC 2010

T2 - 2010 International SoC Design Conference, ISOCC 2010

Y2 - 22 November 2010 through 23 November 2010

ER -

Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application

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