Design Consideration of a Static Memory Cell

Kenji Anami; Masahiko Yoshimoto; Hirofumi Shinohara; Yoshihiro Hirata; Takao Nakano

doi:10.1109/JSSC.1983.1051965

Design Consideration of a Static Memory Cell

Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Yoshihiro Hirata, Takao Nakano

Research output: Contribution to journal › Article › peer-review

32 Citations (Scopus)

Abstract

This paper describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misalignment measured 22.8 × 27.6 µm with 2.5 µm layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

Original language	English
Pages (from-to)	414-418
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	18
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.1983.1051965
Publication status	Published - 1983 Aug
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.1983.1051965

Cite this

@article{29a3c26c2fe545429d3ca9ecf7e09939,

title = "Design Consideration of a Static Memory Cell",

abstract = "This paper describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misalignment measured 22.8 × 27.6 µm with 2.5 µm layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.",

author = "Kenji Anami and Masahiko Yoshimoto and Hirofumi Shinohara and Yoshihiro Hirata and Takao Nakano",

year = "1983",

month = aug,

doi = "10.1109/JSSC.1983.1051965",

language = "English",

volume = "18",

pages = "414--418",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Design Consideration of a Static Memory Cell

AU - Anami, Kenji

AU - Yoshimoto, Masahiko

AU - Shinohara, Hirofumi

AU - Hirata, Yoshihiro

AU - Nakano, Takao

PY - 1983/8

Y1 - 1983/8

N2 - This paper describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misalignment measured 22.8 × 27.6 µm with 2.5 µm layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

AB - This paper describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misalignment measured 22.8 × 27.6 µm with 2.5 µm layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

UR - http://www.scopus.com/inward/record.url?scp=0020797067&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0020797067&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1983.1051965

DO - 10.1109/JSSC.1983.1051965

M3 - Article

AN - SCOPUS:0020797067

SN - 0018-9200

VL - 18

SP - 414

EP - 418

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

ER -

Design Consideration of a Static Memory Cell

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this