Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi; Kenichi Imamiya; Koji Sakui

doi:10.1109/6104.895068

Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi^*, Kenichi Imamiya, Koji Sakui

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

Original language	English
Pages (from-to)	246-254
Number of pages	9
Journal	IEEE Transactions on Electronics Packaging Manufacturing
Volume	23
Issue number	4
DOIs	https://doi.org/10.1109/6104.895068
Publication status	Published - 2000
Externally published	Yes

Keywords

Contact hole diffusion
Device simulation
Drain spacing
ESD
HBM
Lateral npn bipolar protection
MM
Nonsilicided junction
STI

ASJC Scopus subject areas

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/6104.895068

Cite this

@article{7419d9baebba42ce9878253c39110668,

title = "Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory",

abstract = "With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.",

keywords = "Contact hole diffusion, Device simulation, Drain spacing, ESD, HBM, Lateral npn bipolar protection, MM, Nonsilicided junction, STI",

author = "Tamio Ikehashi and Kenichi Imamiya and Koji Sakui",

year = "2000",

doi = "10.1109/6104.895068",

language = "English",

volume = "23",

pages = "246--254",

journal = "IEEE Transactions on Electronics Packaging Manufacturing",

issn = "1521-334X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory

AU - Ikehashi, Tamio

AU - Imamiya, Kenichi

AU - Sakui, Koji

PY - 2000

Y1 - 2000

N2 - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

AB - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

KW - Contact hole diffusion

KW - Device simulation

KW - Drain spacing

KW - ESD

KW - HBM

KW - Lateral npn bipolar protection

KW - MM

KW - Nonsilicided junction

KW - STI

UR - http://www.scopus.com/inward/record.url?scp=0034290346&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034290346&partnerID=8YFLogxK

U2 - 10.1109/6104.895068

DO - 10.1109/6104.895068

M3 - Article

AN - SCOPUS:0034290346

SN - 1521-334X

VL - 23

SP - 246

EP - 254

JO - IEEE Transactions on Electronics Packaging Manufacturing

JF - IEEE Transactions on Electronics Packaging Manufacturing

IS - 4

ER -

Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

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