Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera

doi:10.1109/SOCC.2014.6948897

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

Shinichi Nishizawa^*, Tohru Ishihara, Hidetoshi Onodera

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.

Original language	English
Title of host publication	International System on Chip Conference
Editors	Ramalingam Sridhar, Danella Zhao, Kaijian Shi, Thomas Buchner
Publisher	IEEE Computer Society
Pages	42-47
Number of pages	6
ISBN (Electronic)	9781479933785
DOIs	https://doi.org/10.1109/SOCC.2014.6948897
Publication status	Published - 2014 Nov 5
Externally published	Yes
Event	27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States Duration: 2014 Sept 2 → 2014 Sept 5

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	27th IEEE International System on Chip Conference, SOCC 2014
Country/Territory	United States
City	Las Vegas
Period	14/9/2 → 14/9/5

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2014.6948897

Cite this

Nishizawa, S., Ishihara, T., & Onodera, H. (2014). Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. In R. Sridhar, D. Zhao, K. Shi, & T. Buchner (Eds.), International System on Chip Conference (pp. 42-47). Article 6948897 (International System on Chip Conference). IEEE Computer Society. https://doi.org/10.1109/SOCC.2014.6948897

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. / Nishizawa, Shinichi; Ishihara, Tohru; Onodera, Hidetoshi.
International System on Chip Conference. ed. / Ramalingam Sridhar; Danella Zhao; Kaijian Shi; Thomas Buchner. IEEE Computer Society, 2014. p. 42-47 6948897 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nishizawa, S, Ishihara, T & Onodera, H 2014, Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. in R Sridhar, D Zhao, K Shi & T Buchner (eds), International System on Chip Conference., 6948897, International System on Chip Conference, IEEE Computer Society, pp. 42-47, 27th IEEE International System on Chip Conference, SOCC 2014, Las Vegas, United States, 14/9/2. https://doi.org/10.1109/SOCC.2014.6948897

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abstract = "This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.",

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AB - This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.

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Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

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