TY - GEN
T1 - Design optimization of copper patterns and location of power semiconductors and terminals
AU - Abe, Yusuke
AU - Hirao, Akira
AU - Kato, Ryoichi
AU - Ikeda, Yoshinari
AU - Parque, Victor
AU - Faiz, Muhammad Khairi
AU - Yoshida, Makoto
AU - Miyashita, Tomoyuki
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Energy systems of an Internet of Energy (IoE) society” (Funding agency: JST).
Publisher Copyright:
© 2021 IEEE.
PY - 2021/5/12
Y1 - 2021/5/12
N2 - In recent years, SiC power modules have attracted a lot of attention because they offer higher frequency and density as compared to the conventional Si power module. However high speed switching inevitably lead to the generation of surge voltage which may damage the power module. The design of layout, which composed of copper patterns, power semiconductors and terminals, is one of the factors that is necessary to overcome the problem. In this paper, the layout design of the half-bridge power module is optimized to reduce its internal inductance. The inductance was evaluated by electromagnetic field simulation.
AB - In recent years, SiC power modules have attracted a lot of attention because they offer higher frequency and density as compared to the conventional Si power module. However high speed switching inevitably lead to the generation of surge voltage which may damage the power module. The design of layout, which composed of copper patterns, power semiconductors and terminals, is one of the factors that is necessary to overcome the problem. In this paper, the layout design of the half-bridge power module is optimized to reduce its internal inductance. The inductance was evaluated by electromagnetic field simulation.
KW - Inductance
KW - Layout optimization
KW - Power module
UR - http://www.scopus.com/inward/record.url?scp=85113287928&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85113287928&partnerID=8YFLogxK
U2 - 10.23919/ICEP51988.2021.9451973
DO - 10.23919/ICEP51988.2021.9451973
M3 - Conference contribution
AN - SCOPUS:85113287928
T3 - 2021 International Conference on Electronics Packaging, ICEP 2021
SP - 157
EP - 158
BT - 2021 International Conference on Electronics Packaging, ICEP 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th International Conference on Electronics Packaging, ICEP 2021
Y2 - 12 May 2021 through 14 May 2021
ER -