Periodically all-in-phase clocking (8-step frequency increments with a 4.5ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2X throughput increase are confirmed.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2005|
|Event||2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States|
Duration: 2005 Feb 6 → 2005 Feb 10
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering