Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Koichi Nose; Atsufumi Shibayama; Hiroshi Kodama; Masayuki Mizuno; Masato Edahiro; Naoki Nishi

Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Koichi Nose^*, Atsufumi Shibayama, Hiroshi Kodama, Masayuki Mizuno, Masato Edahiro, Naoki Nishi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

Periodically all-in-phase clocking (8-step frequency increments with a 4.5ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2X throughput increase are confirmed.

Original language	English
Article number	16.3
Pages (from-to)	238-239+618
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
Publication status	Published - 2005
Externally published	Yes
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2005 Feb 6 → 2005 Feb 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs. / Nose, Koichi; Shibayama, Atsufumi; Kodama, Hiroshi et al.
In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 48, 16.3, 2005, p. 238-239+618.

Research output: Contribution to journal › Conference article › peer-review

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title = "Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs",

abstract = "Periodically all-in-phase clocking (8-step frequency increments with a 4.5ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2X throughput increase are confirmed.",

author = "Koichi Nose and Atsufumi Shibayama and Hiroshi Kodama and Masayuki Mizuno and Masato Edahiro and Naoki Nishi",

year = "2005",

language = "English",

volume = "48",

pages = "238--239+618",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "2005 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2005 Through 10-02-2005",

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T1 - Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

AU - Nose, Koichi

AU - Shibayama, Atsufumi

AU - Kodama, Hiroshi

AU - Mizuno, Masayuki

AU - Edahiro, Masato

AU - Nishi, Naoki

PY - 2005

Y1 - 2005

N2 - Periodically all-in-phase clocking (8-step frequency increments with a 4.5ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2X throughput increase are confirmed.

AB - Periodically all-in-phase clocking (8-step frequency increments with a 4.5ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2X throughput increase are confirmed.

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M3 - Conference article

AN - SCOPUS:28144444931

SN - 0193-6530

VL - 48

SP - 238-239+618

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

M1 - 16.3

T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

ER -

Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Abstract

ASJC Scopus subject areas

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