Double charge pump circuit with triple charge sharing clock scheme

Mengshu Huang; Yimeng Zhang; Hao Zhang; Tsutomu Yoshihara

doi:10.1109/ASICON.2011.6157139

Double charge pump circuit with triple charge sharing clock scheme

Mengshu Huang^*, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A double charge pump circuit with triple charge sharing clock scheme is described. The proposed charge sharing clock generator is able to recover nearly two-thirds of the charge from the parasitics charging, in which way the dynamic power loss in the pumping process is reduced to almost one-third. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the double charge pump to achieve a between-branch charge sharing. Under 0.18μm technology with a bottom plate parasitic ratio of 0.2, the simulation results of a proposed 5-stage charge pump circuit show an overall efficiency increase with a peak value of 62.8% comparing to 46.8% of a conventional one, and the output ripple voltage is reduced by nearly a half.

Original language	English
Title of host publication	Proceedings of International Conference on ASIC
Pages	128-132
Number of pages	5
DOIs	https://doi.org/10.1109/ASICON.2011.6157139
Publication status	Published - 2011
Event	2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen Duration: 2011 Oct 25 → 2011 Oct 28

Other

Other	2011 IEEE 9th International Conference on ASIC, ASICON 2011
City	Xiamen
Period	11/10/25 → 11/10/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2011.6157139

Cite this

@inproceedings{f4797727a4394657a7b0b0b2b4ecde0f,

title = "Double charge pump circuit with triple charge sharing clock scheme",

abstract = "A double charge pump circuit with triple charge sharing clock scheme is described. The proposed charge sharing clock generator is able to recover nearly two-thirds of the charge from the parasitics charging, in which way the dynamic power loss in the pumping process is reduced to almost one-third. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the double charge pump to achieve a between-branch charge sharing. Under 0.18μm technology with a bottom plate parasitic ratio of 0.2, the simulation results of a proposed 5-stage charge pump circuit show an overall efficiency increase with a peak value of 62.8% comparing to 46.8% of a conventional one, and the output ripple voltage is reduced by nearly a half.",

author = "Mengshu Huang and Yimeng Zhang and Hao Zhang and Tsutomu Yoshihara",

year = "2011",

doi = "10.1109/ASICON.2011.6157139",

language = "English",

isbn = "9781612841908",

pages = "128--132",

booktitle = "Proceedings of International Conference on ASIC",

note = "2011 IEEE 9th International Conference on ASIC, ASICON 2011 ; Conference date: 25-10-2011 Through 28-10-2011",

}

TY - GEN

T1 - Double charge pump circuit with triple charge sharing clock scheme

AU - Huang, Mengshu

AU - Zhang, Yimeng

AU - Zhang, Hao

AU - Yoshihara, Tsutomu

PY - 2011

Y1 - 2011

N2 - A double charge pump circuit with triple charge sharing clock scheme is described. The proposed charge sharing clock generator is able to recover nearly two-thirds of the charge from the parasitics charging, in which way the dynamic power loss in the pumping process is reduced to almost one-third. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the double charge pump to achieve a between-branch charge sharing. Under 0.18μm technology with a bottom plate parasitic ratio of 0.2, the simulation results of a proposed 5-stage charge pump circuit show an overall efficiency increase with a peak value of 62.8% comparing to 46.8% of a conventional one, and the output ripple voltage is reduced by nearly a half.

AB - A double charge pump circuit with triple charge sharing clock scheme is described. The proposed charge sharing clock generator is able to recover nearly two-thirds of the charge from the parasitics charging, in which way the dynamic power loss in the pumping process is reduced to almost one-third. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the double charge pump to achieve a between-branch charge sharing. Under 0.18μm technology with a bottom plate parasitic ratio of 0.2, the simulation results of a proposed 5-stage charge pump circuit show an overall efficiency increase with a peak value of 62.8% comparing to 46.8% of a conventional one, and the output ripple voltage is reduced by nearly a half.

UR - http://www.scopus.com/inward/record.url?scp=84860876677&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84860876677&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2011.6157139

DO - 10.1109/ASICON.2011.6157139

M3 - Conference contribution

AN - SCOPUS:84860876677

SN - 9781612841908

SP - 128

EP - 132

BT - Proceedings of International Conference on ASIC

T2 - 2011 IEEE 9th International Conference on ASIC, ASICON 2011

Y2 - 25 October 2011 through 28 October 2011

ER -

Double charge pump circuit with triple charge sharing clock scheme

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this