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DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.
K. Tsukamoto*, M. Shimizu, M. Inuishi, Y. Matsuda, H. Oda, H. Morita, M. Nakajima, K. Kobayashi, Y. Mashiko, Y. Akasaka
*Corresponding author for this work
Research output: Contribution to journal › Conference article › peer-review
6
Citations
(Scopus)