Effective post-BIST fault diagnosis for multiple faults

Hiroshi Takahashi*, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.

Original languageEnglish
Title of host publicationProceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages109-117
Number of pages9
ISBN (Print)076952706X, 9780769527062
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, United States
Duration: 2006 Oct 42006 Oct 6

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Country/TerritoryUnited States
CityArlington, VA
Period06/10/406/10/6

ASJC Scopus subject areas

  • General Engineering

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