Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications

Yang Song; Takeshi Ikenaga; Satoshi Goto; Zhenyu Liu

doi:10.1109/APCCAS.2006.342386

Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications

Yang Song^*, Takeshi Ikenaga, Satoshi Goto, Zhenyu Liu

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an enhanced partial distortion sorting (EPDS) fast motion estimation (ME) algorithm which is based on the previous partial distortion sorting (PDS) algorithm. Different to PDS which has fixed parameters, in the EPDS algorithm, these parameters are adaptively adjusted to further reduce the computation complexity. Experiments show that the proposed EPDS algorithm has almost the same image quality as PDS but with 30.72% computation reduction. The PDS and EPDS are both realized in 1-D systolic array, under the worst working conditions (1.62V, 125°C) and 166MHz clock frequency, compared with PDS algorithm, the proposed EPDS algorithm can reduce 15.75% power consumption with 0.75K gates hardware increase.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	1236-1239
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342386
Publication status	Published - 2006 Dec 1
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 2006 Dec 4 → 2006 Dec 6

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	06/12/4 → 06/12/6

Keywords

Motion estimation
Partial distortion sorting

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2006.342386

Cite this

Song, Y., Ikenaga, T., Goto, S., & Liu, Z. (2006). Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1236-1239). Article 4145623 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342386

Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications. / Song, Yang; Ikenaga, Takeshi; Goto, Satoshi et al.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 1236-1239 4145623 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Song, Y, Ikenaga, T, Goto, S & Liu, Z 2006, Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145623, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1236-1239, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06/12/4. https://doi.org/10.1109/APCCAS.2006.342386

@inproceedings{817c999716f44bef91e51db434671310,

title = "Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications",

abstract = "This paper presents an enhanced partial distortion sorting (EPDS) fast motion estimation (ME) algorithm which is based on the previous partial distortion sorting (PDS) algorithm. Different to PDS which has fixed parameters, in the EPDS algorithm, these parameters are adaptively adjusted to further reduce the computation complexity. Experiments show that the proposed EPDS algorithm has almost the same image quality as PDS but with 30.72% computation reduction. The PDS and EPDS are both realized in 1-D systolic array, under the worst working conditions (1.62V, 125°C) and 166MHz clock frequency, compared with PDS algorithm, the proposed EPDS algorithm can reduce 15.75% power consumption with 0.75K gates hardware increase.",

keywords = "Motion estimation, Partial distortion sorting",

author = "Yang Song and Takeshi Ikenaga and Satoshi Goto and Zhenyu Liu",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2006.342386",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1236--1239",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

}

TY - GEN

T1 - Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications

AU - Song, Yang

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

AU - Liu, Zhenyu

PY - 2006/12/1

Y1 - 2006/12/1

N2 - This paper presents an enhanced partial distortion sorting (EPDS) fast motion estimation (ME) algorithm which is based on the previous partial distortion sorting (PDS) algorithm. Different to PDS which has fixed parameters, in the EPDS algorithm, these parameters are adaptively adjusted to further reduce the computation complexity. Experiments show that the proposed EPDS algorithm has almost the same image quality as PDS but with 30.72% computation reduction. The PDS and EPDS are both realized in 1-D systolic array, under the worst working conditions (1.62V, 125°C) and 166MHz clock frequency, compared with PDS algorithm, the proposed EPDS algorithm can reduce 15.75% power consumption with 0.75K gates hardware increase.

AB - This paper presents an enhanced partial distortion sorting (EPDS) fast motion estimation (ME) algorithm which is based on the previous partial distortion sorting (PDS) algorithm. Different to PDS which has fixed parameters, in the EPDS algorithm, these parameters are adaptively adjusted to further reduce the computation complexity. Experiments show that the proposed EPDS algorithm has almost the same image quality as PDS but with 30.72% computation reduction. The PDS and EPDS are both realized in 1-D systolic array, under the worst working conditions (1.62V, 125°C) and 166MHz clock frequency, compared with PDS algorithm, the proposed EPDS algorithm can reduce 15.75% power consumption with 0.75K gates hardware increase.

KW - Motion estimation

KW - Partial distortion sorting

UR - http://www.scopus.com/inward/record.url?scp=50249188281&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50249188281&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2006.342386

DO - 10.1109/APCCAS.2006.342386

M3 - Conference contribution

AN - SCOPUS:50249188281

SN - 1424403871

SN - 9781424403875

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 1236

EP - 1239

BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Enhanced partial distortion sorting fast motion estimation algorithm for low-power applications

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this