Experimental 256-Mb DRAM with boosted sense-ground scheme

Mikio Asakura; Tsukasa Ooishi; Masaki Tsukude; Shigeki Tomishima; Takahisa Eimori; Hideto Hidaka; Yoshikazu Ohno; Kazutani Arimoto; Kazuyasu Fujishima; Tadashi Nishimura; Tsutomu Yoshihara

doi:10.1109/4.328628

Experimental 256-Mb DRAM with boosted sense-ground scheme

Mikio Asakura^*, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm² and a performance of 34 ns access time.

Original language	English
Pages (from-to)	1303-1309
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	29
Issue number	11
DOIs	https://doi.org/10.1109/4.328628
Publication status	Published - 1994 Nov
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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@article{0786d351c18c4548bcf402b689b5ef0b,

title = "Experimental 256-Mb DRAM with boosted sense-ground scheme",

abstract = "In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.",

author = "Mikio Asakura and Tsukasa Ooishi and Masaki Tsukude and Shigeki Tomishima and Takahisa Eimori and Hideto Hidaka and Yoshikazu Ohno and Kazutani Arimoto and Kazuyasu Fujishima and Tadashi Nishimura and Tsutomu Yoshihara",

year = "1994",

month = nov,

doi = "10.1109/4.328628",

language = "English",

volume = "29",

pages = "1303--1309",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - Experimental 256-Mb DRAM with boosted sense-ground scheme

AU - Asakura, Mikio

AU - Ooishi, Tsukasa

AU - Tsukude, Masaki

AU - Tomishima, Shigeki

AU - Eimori, Takahisa

AU - Hidaka, Hideto

AU - Ohno, Yoshikazu

AU - Arimoto, Kazutani

AU - Fujishima, Kazuyasu

AU - Nishimura, Tadashi

AU - Yoshihara, Tsutomu

PY - 1994/11

Y1 - 1994/11

N2 - In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.

AB - In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.

UR - http://www.scopus.com/inward/record.url?scp=0028538213&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028538213&partnerID=8YFLogxK

U2 - 10.1109/4.328628

DO - 10.1109/4.328628

M3 - Article

AN - SCOPUS:0028538213

SN - 0018-9200

VL - 29

SP - 1303

EP - 1309

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 11

ER -

Experimental 256-Mb DRAM with boosted sense-ground scheme

Abstract

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