Experimental demonstration of scalability in a cavity-free planar silicon-integrated thermoelectric device

Shuhei Arai*, Takuya Miura, Md Mehdee Hasan Mahfuz, Takeo Matsuki, Yuma Miyake, Ryuichirou Arayama, Takanobu Watanabe

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

We demonstrate the scalability of cavity-free planar integrated thermoelectric (TE) devices using silicon nanowires (Si-NWs), where miniaturizing the thermoelement by shortening the Si-NWs improves the areal power density. Shortening the Si-NW length decreases the temperature difference between the Si-NW ends and the open-circuit voltage. Meanwhile, the integrated number density of the thermoelement is increased by shortening the Si-NW length, thereby preserving the total electrical resistance. Bileg devices comprising both n- and p-type Si-NWs exhibited superior performance compared to unileg devices comprising only n-type Si-NWs. In unileg devices, the hot and cold electrodes in the adjacent thermoelements are interconnected through metal wiring, which leaks heat, resulting in a lowering of the temperature difference between the Si-NW ends. This study yields structural design guidelines for planar-integrated TE devices using Si-NWs.

Original languageEnglish
Article number02SP38
JournalJapanese journal of applied physics
Volume63
Issue number2
DOIs
Publication statusPublished - 2024 Feb 29

Keywords

  • scalability
  • silicon nanowire
  • thermoelectirc device

ASJC Scopus subject areas

  • General Engineering
  • General Physics and Astronomy

Fingerprint

Dive into the research topics of 'Experimental demonstration of scalability in a cavity-free planar silicon-integrated thermoelectric device'. Together they form a unique fingerprint.

Cite this